Projects

Motion Estimation/Compensation (MEMC)

Course Final Project of Computer-Aided Vlsi System Design

• Adopted down sampling for image pixels, shrunk search range within matching blocks, and early skipping for min-max error.
• Scheduled truncated pixels of separated images into one SRAM and parallelized the computation with 4 process elements.

Miller’s Algorithm in Pairing-Based Cryptography

Course Final Project of Cryptography

• Surveyed algorithmic improvements to decrease the complexity of Miller’s algorithm.

Baby-Step Giant-Step Attack on Diffie-Hellman Key Exchange Protocol

Course Final Project of Integrated Circuits Design Laboratory

• Organized the architecture and instructed team members to accomplish encryption/decryption (DES) and key-exchange protocol (DHKE).
• Implemented Montgomery multiplication/division for arithmetic computation over Galois field.
• Fabricated in 180-nm CMOS technology and validated with measurement results

Frequency Analysis System

Summer Training in Energy-Efficient Circuits and Systems Lab

• Employed transposed finite impulse response filter to shorten the critical path and reduce the number of adders.
• Exploited radix-$2^2$ 16-point FFT to reduce the multiplicative complexity.
• Searched the main frequency with folding architect to share datapath logic.

Parallelism Factor of 2D Convolution Circuit in 28-nm CMOS Technology

Course Final Project of Digital Signal Processing in Vlsi Design

• Evaluated energy efficiency of a convolutional neural network under differet levels of parallelism.

5-Stage Pipelined MIPS

Course Final Project of Digital System Design

• Extended pipelined multiplication/division to shorten critical path and carried Booth’s algorithm to facilitate recursive computation.
• Exploited the advantage of locality through multi-levels of caches with different read/write policies.

Voltage Follower

• Adjusted the MOS parameters in a 2-stage operational amplifier to realize the specified behavior.
• Simulated the design in 180-nm technology.